The present invention relates generally to semiconductor devices and the fabrication thereof and, more particularly, to a semiconductor-on-insulator (SOI) MOSFET having an atrophied source and drain to enhance device performance and a method of fabrication.
A pervasive trend in modem integrated circuit manufacture is to produce semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), that are as small as possible. In a typical MOSFET, a source and a drain are formed in an active region of a semiconductor layer by implanting N-type or P-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a body region. Disposed above the body region is a gate electrode that defines a channel in the body. The gate electrode and the body are spaced apart by a gate dielectric layer. It is noted that MOSFETs can be formed in bulk format (for example, the active region being formed in a silicon substrate) or in a semiconductor-on-insulator (SOI) format (for example, in a silicon film that is disposed on an insulating layer that is, in turn, disposed on a silicon substrate).
The fabrication of smaller transistors, and the placement of transistors as close to one another as possible, allows more transistors to be placed on a single monolithic substrate for the formation of a relatively large circuit system in a relatively small die area. Also, SOI wafers offer potential advantages over bulk wafers for the fabrication of high performance integrated circuits. Dielectric isolation and reduction of parasitic capacitance improve circuit performance, and virtually eliminate latch-up in CMOS circuits. In addition, circuit layout in SOI can be greatly simplified and packing density greatly increased if the devices are made without body contacts (i.e., if the body regions of the devices are xe2x80x9cfloatingxe2x80x9d).
However, MOSFETs formed in SOI format can exhibit parasitic effects due to the presence of the floating body (xe2x80x9cfloating body effectsxe2x80x9d). These floating body effects may result in undesirable performance in SOI devices.
In addition, integrated circuit downscaling by omitting isolation regions between adjacent devices can result in performance degrading effects. In SOI FET devices that are place directly adjacent one another (e.g., the source or drain of one device is located directly adjacent the source or drain of another device with no dielectric material formed therebetween), parasitic leakage from the adjacent floating bodies can diminish circuit performance. One solution to reducing leakage current in such an arrangement has been to increase source/drain implant dosages. However, this solution tends to sacrifice optimization of the source/drain junctions with the body and degradation of device performance has resulted.
Accordingly, there exists a need in the art for semiconductor devices, such as MOSFETs, that optimize scale and performance. There also exists a need for corresponding fabrication techniques to make those semiconductor devices.
According to one aspect of the invention, the invention is directed to an integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.
According to another aspect of the invention, the invention is directed to a method of forming an integrated circuit in semiconductor-on-insulator format. The method includes providing a semiconductor-on-insulator wafer having a layer of semiconductor material disposed on an insulating layer, the insulating layer disposed on a substrate; forming a first gate electrode and a second gate electrode over the layer of semiconductor material, each of the first and the second gate electrode being separated from the layer of semiconductor material by dielectric material; implanting amorphizing ion species into the layer of semiconductor material to form an amorphous semiconductor material portion in the layer of semiconductor material between the first and the second gate electrode and extending from an upper surface of the layer of semiconductor material to the isolating layer; implanting dopant ion species into the layer of semiconductor material to form a first source and a first drain adjacent respective sides of the first gate electrode and one of the first source and the first drain being formed at least in part in the amorphous semiconductor material portion, and to form a second source and a second drain adjacent respective sides of the second gate electrode and one of the first source and the first drain being formed at least in part in the amorphous semiconductor material portion, and wherein the one of the second source and the second drain is disposed adjacent the one of the first source and the first drain; and annealing the wafer to partially recrystallize the amorphous semiconductor material portion to form a crystalline portion of the one of the first source and the first drain, and to form a crystalline portion of the one of the second source and the second drain, wherein an amorphous region remains between the crystalline portion of the one of the first source and the first drain and the crystalline portion of the one of the second source and the second drain.